Nonvolatile semiconductor memory device and method for driving same

ABSTRACT

According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

More than one reissue application has been filed for the reissue of U.S.Pat. No. 8,218,358. The reissue applications are Ser. No. 14/327,359(parent application), and the present continuation application. Thepresent application claims the benefit of priority under 35 U.S.C. § 120of application Ser. No. 14/327,359.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2009-251891, filed on Nov. 2,2009; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a nonvolatilesemiconductor memory device and method for driving the same.

BACKGROUND

Semiconductor memory devices of flash memory and the like conventionallyhave been constructed by two-dimensionally integrating memory cells onthe surface of a silicon substrate. In such a semiconductor memorydevice, it is necessary to increase the integration of the memory cellsto reduce the cost per bit and increase the storage capacity. However,such increases of integration in recent years have become difficult inregard to both cost and technology.

Methods of three-dimensional integration by stacking memory cells havebeen proposed as technology to breakthrough the limitations ofincreasing the integration. However, methods that simply stack andpattern one layer after another undesirably increase the number ofprocesses as the number of stacks increases, and the costs undesirablyincrease. In particular, the increase of lithography processes forpatterning the transistor structure is a main cause of increasing costs.Therefore, the reduction of the chip surface area per bit by stackinghas not led to lower costs per bit as much as downsizing within the chipplane and is problematic as a method for increasing the storagecapacity.

In consideration of such problems, the inventors have proposed acollectively patterned three-dimensionally stacked memory (for instance,refer to JP-A 2007-266143 (Kokai)). In such technology, a stacked bodyincluding electrode films alternately stacked with insulative films isformed on a silicon substrate; and subsequently, through-holes are madein the stacked body by collective patterning. A blocking film, a chargestorage film, and a tunneling film are deposited in this order to form amemory film on the side face of the through-hole; and a silicon pillaris buried in the interior of the through-hole. A memory transistor isthereby formed at an intersection between each electrode film and thesilicon pillar.

In such a collectively patterned three-dimensionally stacked memory, acharge can be removed from and put into the charge storage layer fromthe silicon pillar to store information by controlling an electricalpotential of each electrode film and each silicon pillar. According tosuch technology, the through-holes are made by collectively patterningthe stacked body. Therefore, the number of lithography processes doesnot increase and cost increases can be suppressed even in the case wherethe number of stacks of the electrode films increases.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of features of a nonvolatile semiconductor memorydevice according to a first embodiment;

FIG. 2 is a perspective view of the nonvolatile semiconductor memorydevice according to the first embodiment;

FIG. 3 is a cross-sectional view of the nonvolatile semiconductor memorydevice according to the first embodiment;

FIG. 4 is a circuit diagram of a memory string of the nonvolatilesemiconductor memory device according to the first embodiment;

FIG. 5 is a plan view of electrode films of the nonvolatilesemiconductor memory device according to the first embodiment;

FIG. 6 is a circuit diagram of a drive circuit of the nonvolatilesemiconductor memory device according to the first embodiment;

FIG. 7 is a diagram of potentials applied to each electrode andinterconnections during operations of the nonvolatile semiconductormemory device according to first embodiment;

FIG. 8 is a diagram of potentials applied to control gate electrodes ofeach level during operations of the nonvolatile semiconductor memorydevice according to the first embodiment;

FIG. 9 is a graph of a method for determining a potential to be applied,where the diameter of a through-hole is plotted on the horizontal axisand the potential difference between a control gate electrode and asilicon pillar is plotted on the vertical axis;

FIG. 10 a diagram of features of a nonvolatile semiconductor memorydevice according to a second embodiment;

FIG. 11 is a cross-sectional view of processes of a method formanufacturing a nonvolatile semiconductor memory device according to athird embodiment;

FIG. 12 is a cross-sectional view of processes of the method formanufacturing a nonvolatile semiconductor memory device according to thethird embodiment;

FIG. 13 is a cross-sectional view of processes of the method formanufacturing a nonvolatile semiconductor memory device according to thethird embodiment;

FIG. 14 is a cross-sectional view of processes of the method formanufacturing a nonvolatile semiconductor memory device according to thethird embodiment;

FIG. 15 is a cross-sectional view of processes of the method formanufacturing a nonvolatile semiconductor memory device according to thethird embodiment;

FIG. 16 is a cross-sectional view of processes of the method formanufacturing a nonvolatile semiconductor memory device according to thethird embodiment;

FIG. 17 is a cross-sectional view of processes of the method formanufacturing a nonvolatile semiconductor memory device according to thethird embodiment;

FIG. 18 is a cross-sectional view of processes of the method formanufacturing a nonvolatile semiconductor memory device according to thethird embodiment; and

FIG. 19 is a cross-sectional view of processes of the method formanufacturing a nonvolatile semiconductor memory device according to thethird embodiment.

DETAILED DESCRIPTION

In general, according to one embodiment, a nonvolatile semiconductormemory device includes a substrate, a stacked body, a semiconductorpillar, a charge storage film, and a drive circuit. The stacked body isprovided on the substrate. The stacked body includes a plurality ofinsulating films alternately stacked with a plurality of electrodefilms. A through-hole is made in the stacked body to align in a stackingdirection. The semiconductor pillar is buried in an interior of thethrough-hole. The charge storage film is provided between the electrodefilm and the semiconductor pillar. The drive circuit supplies apotential to the electrode film. The diameter of the through-holediffers by a position in the stacking direction. The drive circuitsupplies a potential to reduce a potential difference with thesemiconductor pillar as a diameter of the through-hole piercing theelectrode film decreases.

Exemplary embodiments will now be described with reference to thedrawings.

First, a first embodiment of the invention will be described.

FIG. 1 schematically illustrates features of a nonvolatile semiconductormemory device according to this embodiment.

FIG. 2 is a perspective view illustrating the nonvolatile semiconductormemory device according to this embodiment.

FIG. 3 is a cross-sectional view illustrating the nonvolatilesemiconductor memory device according to this embodiment.

FIG. 4 is a circuit diagram illustrating a memory string of thenonvolatile semiconductor memory device according to this embodiment.

FIG. 5 is a plan view illustrating electrode films of the nonvolatilesemiconductor memory device according to this embodiment.

FIG. 6 is a circuit diagram illustrating a drive circuit of thenonvolatile semiconductor memory device according to this embodiment.

For easier viewing of the drawings in FIG. 1 and FIG. 2, only theconductive portions are illustrated, and the insulating portions areomitted. This is similar for FIG. 10 described below. For convenience ofillustration in FIG. 2, the silicon pillars are illustrated with thesame thickness regardless of the Z-direction position.

First, distinctive portions of this embodiment will be summarilydescribed.

As illustrated in FIG. 1, a feature of a nonvolatile semiconductormemory device 1 according to this embodiment is that a drive circuit 41supplying a driving potential to a control gate electrode CG applies thedriving potential to reduce the potential difference with a siliconpillar 31 as a diameter of a through-hole piercing the control gateelectrode CG decreases in a collectively patterned three-dimensionallystacked memory device in which memory transistors are provided atintersections between the silicon pillar 31 and the control gateelectrodes CG. More specifically, in the nonvolatile semiconductormemory device 1, the diameter of the through-hole in which the siliconpillar 31 is buried decreases as the control gate electrode CG isdisposed in a lower level. Therefore, the drive circuit 41 applies alower driving potential to the control gate electrode CG disposed in alower level.

The configuration of the nonvolatile semiconductor memory device willnow be described in detail.

As illustrated in FIG. 2 and FIG. 3, a silicon substrate 11 is providedin the nonvolatile semiconductor memory device 1 (hereinbelow, alsoreferred to as “the device 1”) according to this embodiment. A memorycell region, in which memory cells are formed, and a peripheral circuitregion (not illustrated), in which a drive circuit is formed, are set inthe silicon substrate 11. The peripheral circuit region is disposedaround the memory cell region.

First, the memory cell region will be described.

A feature of the memory cell region is that a stacked body ML, in whichmemory cells are arranged three-dimensionally, is provided. The diameterof a through-hole 21 piercing the stacked body ML becomes finerdownward. The configuration of the memory cell region will now bedescribed in detail.

An insulating film 10 is provided on the silicon substrate 11 in thememory cell region. Thereupon, a conductive film, e.g., a polysiliconfilm 12, is formed to form a back gate BG. Multiple electrode films 14are alternately stacked with multiple insulating films 15 on the backgate BG; and the stacked body ML is formed.

For convenience of description in the specification, an XYZ orthogonalcoordinate system will now be introduced. In this coordinate system, twomutually orthogonal directions parallel to an upper face of the siliconsubstrate 11 are taken as an X direction and a Y direction. A directionorthogonal to both the X direction and the Y direction, that is, thestacking direction of each layer, is taken as a Z direction.

The electrode film 14 is formed of, for example, polysilicon. In anX-direction central portion of the stacked body ML, the electrode film14 is divided along the Y direction to form multiple control gateelectrodes CG aligned in the X direction. Each layer of the electrodefilms 14 is patterned into the same pattern as viewed from above, i.e.,the Z direction. As described below, at both X-direction end portions ofthe stacked body ML, the electrode film 14 is not divided along the Ydirection to form one pair of comb-shaped configurations. On the otherhand, the insulating films 15 are made of, for example, silicon oxide(SiO₂) and function as inter-layer insulating films to insulate theelectrode films 14 from each other.

An insulating film 16, a conductive film 17 and an insulating film 18are formed in this order on the stacked body ML. The conductive film 17is made of, for example, polysilicon, is divided along the Y direction,and forms multiple selection gate electrodes SG aligned in the Xdirection. Two selection gate electrodes SG are provided in the regiondirectly above each of the control gate electrodes CG of the uppermostlayer. That is, although the selection gate electrode SG is aligned inthe same direction (the X direction) as the control gate electrode CG,the arrangement period is half. As described below, the selection gateelectrodes SG include a selection gate electrode SGb on the bit lineside and a selection gate electrode SGs on the source line side.

An insulating film 19 is provided on the insulating film 18. A sourceline SL is provided on the insulating film 19 to align in the Xdirection. The source line SL is disposed in a region directly aboveevery other one of the control gate electrodes CG of the uppermost layerarranged along the Y direction. An insulating film 20 is provided on theinsulating film 19 to cover the source line SL. Multiple bit lines BLare provided on the insulating film 20 to align in the Y direction. Eachof the source lines SL and the bit lines BL are formed of a metal film.

Multiple through-holes 21 are aligned in the stacking direction (the Zdirection) of each of the layers to pierce the stacked body ML. Theconfiguration of the through-hole 21 is, for example, circular as viewedfrom the Z direction. On the other hand, the side face of thethrough-hole 21 inclines with respect to the perpendicular direction;and the through-hole 21 becomes finer downward. Each of thethrough-holes 21 pierces the control gate electrode CG of each of thelevels; and the lower end reaches the back gate BG. The through-holes 21are arranged in a matrix configuration along the X direction and the Ydirection. Because the control gate electrode CG is aligned in the Xdirection, multiple through-holes 21 arranged in the X direction piercethe same control gate electrode CG. The arrangement period of thethrough-holes 21 in the Y direction is half the arrangement period ofthe control gate electrodes CG. Thereby, two of the through-holes 21arranged in the Y direction form one set; and the through-holes 21belonging to the same set pierce the same control gate electrode CG.

A communicating hole 22 is made in an upper layer portion of the backgate BG so that the lower end portion of one through-hole 21communicates with the lower end portion of one other through-hole 21distal one row in the Y direction as viewed from the one through-hole21. Thereby, one continuous U-shaped hole 23 is made of one pair of thethrough-holes 21 adjacent to each other in the Y direction and thecommunicating hole 22 communicating between the pair. Multiple U-shapedholes 23 are made in the stacked body ML.

An ONO (Oxide Nitride Oxide) film 24 is provided on an inner face of theU-shaped hole 23 via a barrier film (not illustrated) made of, forexample, silicon nitride. In the ONO film 24, an insulative blockingfilm 25, a charge storage film 26, and an insulative tunneling film 27are stacked in order from the outside. The blocking film 25 is a film inwhich current substantially does not flow even when a voltage in therange of the drive voltage of the device 1 is applied and is formed of,for example, a high dielectric constant material having a dielectricconstant higher than the dielectric constant of the material forming thecharge storage film 26, e.g., silicon oxide. The charge storage film 26is a film capable of trapping charge and is formed of, for example,silicon nitride. Although the tunneling film 27 normally is insulative,the tunneling film 27 is a film in which a tunneling current flows whena prescribed voltage in the range of the drive voltage of the device 1is applied and is formed of, for example, silicon oxide. The filmthickness of the ONO film 24 is substantially uniform over the entireregion on the inner face of the U-shaped hole 23.

A semiconductor material doped with an impurity, e.g., polysilicon, isfilled into the interior of the U-shaped hole 23. Thereby, a U-shapedsilicon member 33 is provided in the interior of the U-shaped hole 23.The portion of the U-shaped silicon member 33 positioned in thethrough-hole 21 forms the silicon pillar 31; and the portion positionedin the communicating hole 22 forms a connection member 32. The siliconpillar 31 has a columnar configuration, e.g., a circular columnarconfiguration, aligned in the Z direction. However, as described above,the diameter of the through-hole 21 becomes finer downward. Therefore,the diameter of the silicon pillar 31 filled into the interior thereofalso becomes finer downward. The connection member 32 has a columnarconfiguration, e.g., a quadrilateral columnar configuration, aligned inthe Y direction. Two of the silicon pillars 31 and one of the connectionmembers 32 are formed integrally to form the U-shaped silicon member 33.Accordingly, the U-shaped silicon member 33 is formed continuouslywithout breaks along the longitudinal direction thereof. The U-shapedsilicon member 33 is insulated from the back gate BG and the controlgate electrode CG by the ONO film 24.

Multiple through-holes 51 are made in the insulating film 16, theselection gate electrode SG, and the insulating film 18. Each of thethrough-holes 51 is made in a region directly above each of thethrough-holes 21 to communicate with each of the through-holes 21. Here,because the selection gate electrode SG is aligned in the X direction,the through-holes 51 arranged in the X direction pierce the sameselection gate electrode SG. The arrangement period of the through-hole51 in the Y direction is the same as the arrangement period of theselection gate electrode SG with the same arrangement phase.Accordingly, one of the multiple through-holes 51 arranged in the Ydirection corresponds to one of the selection gate electrodes SG; andthe multiple through-holes 51 pierce mutually different selection gateelectrodes SG.

A gate insulating film 28 is formed on the inner face of thethrough-hole 51. Polysilicon, for example, is filled into the interiorof the through-hole 51 to form a silicon pillar 34. The silicon pillar34 has a columnar configuration, e.g., a circular columnarconfiguration, aligned in the Z direction. The lower end portion of thesilicon pillar 34 is connected to the upper end portion of the siliconpillar 31 formed in a region directly therebelow. The silicon pillar 34is insulated from the selection gate electrode SG by the gate insulatingfilm 28. A U-shaped pillar 30 is formed of the U-shaped silicon member33 and the pair of silicon pillars 34 connected to the upper endportions thereof.

The positional relationship among the U-shaped pillar 30, the controlgate electrode CG, the selection gate electrode SG, the source line SL,and the bit line BL will now be described. One pair of the siliconpillars 34 and 31 adjacent in the Y direction is connected to each otherby the connection member 32 to form the U-shaped pillar 30. On the otherhand, the control gate electrode CG, the selection gate electrode SG,and the source line SL are aligned in the X direction; and the bit lineBL is aligned in the Y direction. Although the arrangement periods ofthe U-shaped pillar 30 and the control gate electrode CG in the Ydirection are the same, the phases are shifted one half-period.Therefore, one pair of the silicon pillars 31 belonging to each of theU-shaped pillars 30, i.e., the two silicon pillars 31 connected to eachother by the connection member 32, pierces mutually different controlgate electrodes CG. On the other hand, two silicon pillars 31 mutuallyadjacent in the Y direction and belonging to two U-shaped pillars 30mutually adjacent in the Y direction pierce a common control gateelectrode CG.

The multiple silicon pillars 34 arranged in the Y direction piercemutually different selection gate electrodes SG. Accordingly, one pairof silicon pillars 34 belonging to each of the U-shaped pillars 30pierces mutually different selection gate electrodes SG. On the otherhand, the multiple U-shaped pillars 30 arranged in the X directionpierce a common pair of selection gate electrodes SG.

One silicon pillar 34 of the pair of silicon pillars 34 belonging toeach of the U-shaped pillars 30 is connected to the source line SL via asource plug SP buried in the insulating film 19; and one other siliconpillar 34 of the pair is connected to the bit line BL via a bit plug BPburied in the insulating films 19 and 20. Accordingly, the U-shapedpillar 30 is connected between the bit line BL and the source line SL.In FIG. 1 to FIG. 4, the selection gate electrode SG pierced by theU-shaped pillar 30 and disposed on the bit line side is illustrated asthe selection gate electrode SGb; and the selection gate electrode SGpierced by the U-shaped pillar 30 and disposed on the source line sideis illustrated as the selection gate electrode SGs. The U-shaped pillars30 arranged in the X direction are connected to a common source line SLand to mutually different bit lines BL. Here, the arrangement period ofthe U-shaped pillar 30 in the X direction is the same as the arrangementperiod of the bit line BL. Therefore, in the X direction, the U-shapedpillar 30 and the bit line BL correspond one-to-one. On the other hand,two of the U-shaped pillars 30 arranged in the Y direction are connectedto each of the source lines SL as one set and are connected to a commonbit line BL.

In the device 1 as illustrated in FIG. 1 to FIG. 4, the silicon pillar31 functions as a channel and the control gate electrode CG functions asa gate electrode. Thereby, a vertical memory transistor 35 is formed atthe intersection between the silicon pillar 31 and the control gateelectrode CG. Each of the memory transistors 35 functions as a memorycell by the charge storage film 26 disposed between the silicon pillar31 and the control gate electrode CG storing electrons. In the stackedbody ML, the multiple silicon pillars 31 are arranged in a matrixconfiguration along the X direction and the Y direction. Therefore, themultiple memory transistors 35 are arranged three-dimensionally alongthe X direction, the Y direction, and the Z direction.

A selection transistor 36 is formed at the intersection between thesilicon pillar 34 and the selection gate electrode SG with the siliconpillar 34 as the channel, the selection gate electrode SG as the gateelectrode, and the gate insulating film 28 as the gate insulating film.The selection transistor 36 is a vertical transistor similar to thememory transistor 35 described above.

Also, because the ONO film 24 is interposed between the connectionmember 32 and the back gate BG, a back gate transistor 37 is formed withthe connection member 32 as the channel, the back gate BG as the gateelectrode, and the ONO film 24 as the gate insulating film. In otherwords, the back gate BG functions as an electrode to control theconducting state of the connection member 32 by an electric field.

As a result, as illustrated in FIG. 4, a memory string 38 connectedbetween the bit line BL and the source line SL along each of theU-shaped pillars 30 is formed. In the memory string 38, the selectiontransistor 36 is provided at both end portions; the back gate transistor37 is provided in the central portion; and the same number of memorytransistors 35 as the number of stacks of the electrode films 14 isconnected in series between the back gate transistor 37 and each of theselection transistors 36. In other words, the multiple memorytransistors 35 arranged three-dimensionally in the stacked body ML maybe collected as the memory string 38 for each of the U-shaped siliconmembers 33.

As illustrated in FIG. 5, the memory cell region of the device 1 isdivided into multiple blocks 50. The positional relationship between theblock 50 and each of the conductive members will now be described.

As illustrated in FIG. 5, the multiple blocks 50 set in the memory cellregion are arranged along the Y direction. The conductive membersprovided in the device 1 to align in the X direction, i.e., the controlgate electrode CG and the selection gate electrode SG, and the U-shapedpillar 30 aligned in the Z direction are organized into each of theblocks 50. The back gate BG formed along the XY plane is subdivided andmutually separated electrically from each other for each of the blocks50. On the other hand, the bit line BL aligned in the Y directionextends to pass through all of the blocks 50 and is common to all of theblocks 50. An element separation film (not illustrated) is formed in aregion of the silicon substrate 11 between the blocks 50.

The control gate electrodes CG belonging to each of the blocks 50 areorganized further into two groups. In other words, the control gateelectrodes CG are divided into the control gate electrode CG disposed ina region directly below the source line SL and pierced by the siliconpillar having an upper end portion connected to the source line SL(illustrated as a control gate electrode CGs in FIG. 5) and the controlgate electrode CG disposed in a region outside of the region directlybelow the source line SL and pierced by a silicon pillar having an upperend portion connected to the bit line BL (illustrated as a control gateelectrode CGb in FIG. 5). The control gate electrodes CGs and thecontrol gate electrodes CGb are alternately arranged along the Ydirection; the control gate electrodes CGs are commonly connected toeach other; and the control gate electrodes CGb are commonly connectedto each other. The control gate electrodes CGs are electricallyseparated from the control gate electrodes CGb.

Specifically, as illustrated in FIG. 5, the electrode films 14(referring to FIG. 1) are not divided along the Y direction at both ofthe X-direction end portions of the stacked body ML; and incisionsaligned in the X direction are made intermittently. Thereby, in each ofthe blocks 50, the electrode films 14 are subdivided into a pair ofmutually meshed comb-shaped patterns to form the control gate electrodesCGs and the control gate electrodes CGb, respectively. Although thecontrol gate electrode CGs has three comb teeth and the control gateelectrode CGb has two comb teeth in FIG. 5 to simplify the drawing, thisembodiment is not limited thereto, and the number of comb teeth may behigher.

The peripheral circuit region will now be described.

As illustrated in FIG. 6, the drive circuit 41 is provided in theperipheral circuit region to drive the memory string 38. The drivecircuit 41 includes a potential supply unit 42b that applies a drivingpotential to the control gate electrode CGb of each of the levels formedin the stacked body ML and the selection gate electrode SGb, a potentialsupply unit 42s that applies a driving potential to the control gateelectrode CGs of each of the levels and the selection gate electrodeSGs, and a decoder 43 that outputs a control signal.

A pump circuit unit 44 is provided in the potential supply unit 42b. Thepump circuit unit 44 includes n pump circuits 45(1) to 45(n), where n isthe number of levels of the electrode films 14. Each of the pumpcircuits 45 is a circuit that increases the supplied voltage by aprescribed amount, where the voltage increase amount is different foreach of the pump circuits.

A switch circuit unit 46 is provided in the potential supply unit 42b.The switch circuit unit 46 includes n switch elements 47(1) to 47(n).One end of a switch element 47(k) is connected to a pump circuit 45(k)and the other end is connected to the control gate electrode CGb of thekth level from the bottom of the stacked body ML, where k is an integerfrom 1 to n. Based on a control signal output by the decoder 43, theswitch element 47(k) switches to connect or disconnect the pump circuit45(k) and the control gate electrode CGb of the kth level from thebottom. For example, each of switch elements 47 is formed of a MOSFET;one of the source and drain is connected to the pump circuit 45; theother is connected to the control gate electrode CGb; and the gate iscommonly connected to an output terminal of the decoder 43. Thereby, thepump circuit 45 is connected to the control gate electrode CGb only forthe interval in which the decoder 43 outputs the prescribed controlsignal.

The configuration of the potential supply unit 42s also is similar tothat of the potential supply unit 42b. In other words, the potentialsupply unit 42s also includes the pump circuit unit 44 and the switchcircuit unit 46; and each of the switch elements 47 connect each of thepump circuits 45 to each of the control gate electrodes CGs based on acontrol signal output by the decoder 43.

Operations of the nonvolatile semiconductor memory device 1 according tothis embodiment having the configuration described above will now bedescribed.

FIG. 7 illustrates the potentials applied to the electrodes and theinterconnections during operations of the nonvolatile semiconductormemory device according to this embodiment.

FIG. 8 illustrates the potentials applied to the control gate electrodesof each of the levels during operations of the nonvolatile semiconductormemory device according to this embodiment.

FIG. 9 is a graph illustrating a method for determining the potential tobe applied, where the diameter of the through-hole is plotted on thehorizontal axis and the potential difference between the control gateelectrode and the silicon pillar is plotted on the vertical axis.

In the following description, the memory transistor 35 is taken to be ann-channel field effect transistor. In the memory transistor 35, thestate in which electrons are stored in the charge storage film 26 andthe threshold value is shifted to positive is taken to be the value “0;”and the state in which electrons are not stored in the charge storagefilm 26 and the threshold value is not shifted is taken to be the value“1.” The number of levels (n) of the control gate electrodes is taken tobe 4. The memory transistor 35 (hereinbelow referred to as “selectedcell”) to and from which data is to be written and read is taken to bethe memory transistor of the third level from the bottom of the siliconpillar having an upper end portion connected to the bit line BL. Inother words, the control gate electrode CGb of the third level from thebottom is the gate electrode of the selected cell. Further, it is takenthat in the initial state, electrons are not stored in any of the memorytransistors 35. Accordingly, the value “1” is written thereto.

(Writing Operation)

First, writing operations to write any data to each of the memorytransistors 35 will be described. The writing of the date is performedfor one block at a time in order and is performed simultaneously formultiple selected cells arranged in the X direction. As illustrated inFIG. 2, although these multiple selected cells belong to mutuallydifferent memory strings 38, they share the same control gate electrodeCG. Also, although the multiple memory strings 38 to which theseselected cells belong are connected to mutually different bit lines BL,the multiple memory strings 38 pierce a common selection gate electrodeSG and are connected to a common source line SL.

First, the Y coordinate of the memory strings 38 (hereinbelow referredto as “selected strings”) of the memory transistors 35 to be written(the selected cells) is selected. Specifically, as illustrated in FIG.7, the drive circuit 41 applies a selection gate potential V_(sg) to theselection gate electrode SGb of the selected strings and applies an OFFpotential V_(off) to the selection gate electrode SGs. The drive circuit41 applies the OFF potential V_(off) to the selection gate electrodesSGb and SGs of the unselected memory strings 38. The OFF potentialV_(off) is a potential of the gate electrode of the transistor such thatthe transistor is switched to the OFF state, e.g., a reference potentialVss. The reference potential Vss is, for example, a grounding potential(0 V). The selection gate potential V_(sg) is a potential of theselection gate electrode SG of the selection transistor 36 such that theconducting state of the selection transistor 36 is determined by thepotential of the silicon pillar (the body potential), e.g., a potentialhigher than the reference potential Vss. The potential of the back gateBG is taken as an ON potential V_(on). The ON potential V_(on) is apotential of the gate electrode of the transistor such that thetransistor is switched to the ON state, e.g., a power supply potentialVdd (e.g., 3.0 V).

Thereby, the selection transistors 36 on the bit line side of theselected strings are switched to the ON state and the OFF state by thepotential of the bit lines BL; and the selection transistors 36 on thesource line side are switched to the OFF state. All of the selectiontransistors 36 of the unselected memory strings 38 are switched to theOFF state. The back gate transistors 37 of all of the memory strings 38are switched to the ON state.

Then, the reference potential Vss (e.g., 0 V) is applied to the bitlines BL connected to the selected cells to be written with the value“0;” and the power supply potential Vdd (e.g., 3.0 V) is applied to thebit lines BL connected to the selected cells to be written with thevalue “1.” On the other hand, the power supply potential Vdd is appliedto all of the source lines SL.

In this state, the positions of the selected cells of the selectedstrings are selected. Specifically, the drive circuit 41 increases thepotential of the control gate electrode CG of the selected cells, e.g.,the control gate electrodes CGb of the third layer from the bottom, to awriting potential V_(pgm) (e.g., 18 V); and the potential of the othercontrol gate electrodes CG, i.e., the control gate electrodes CGb of thelayers other than the third layer from the bottom and all of the controlgate electrodes CGs, are provided with an intermediate potentialV_(pass) (e.g., 10 V). At this time, because the control gate electrodesCGb of the third layer are connected to each other, the writingpotential V_(pgm) is applied to the control gate electrodes CGb of thethird layer also for the unselected memory strings. The writingpotential V_(pgm) is a potential high enough to inject electrons fromthe silicon pillar 31 into the charge storage film 26 of the ONO film24, and is a potential higher than the reference potential Vss and theselection gate potential V_(sg). That is, Vss<V_(sg)<V_(pgm). Althoughthe intermediate potential V_(pass) is a potential higher than thereference potential Vss, the intermediate potential V_(pass) is apotential lower than the writing potential V_(pgm). That is,Vss<V_(pass)<V_(pgm). However, as described below, the value of thewriting potential V_(pgm) differs by the level where the control gateelectrode CG to which the potential is to be applied is disposed.

Thereby, for the selected cells to be written with the value “0,” thepotential difference between the source potential and the gate potentialof the selection transistors 36 on the bit line side exceeds thethreshold and the selection transistors 36 are switched to the ON statebecause the potential of the bit lines BL is the reference potential Vss(e.g., 0 V) and the potential of the selection gate electrodes SGb onthe bit line side is the selection gate potential V_(sg) which is higherthan the reference potential Vss. As a result, a body potential V_(body)of the selected cells approaches the reference potential Vss. Thepotential of the control gate electrodes CG of the selected cells is thewriting potential V_(pgm) (e.g., 18 V). Accordingly, the difference(V_(pgm)−V_(body)) between the gate potential and the body potential ofthe selected cells is sufficiently large; high-temperature electrons arecreated by the potential difference; and the electrons are injected fromthe silicon pillar 31 into the charge storage film 26 via the tunnelinglayer 27. Thereby, the value “0” is written into the selected cells.

On the other hand, for the selected cells to be written with the value“1,” the potential of the bit lines BL is the positive potential Vdd(e.g., 3.0 V) and the potential of the selection gate electrode SGb onthe bit line side is the selection gate potential V_(sg) which is higherthan the reference potential Vss. Therefore, the potential differencebetween the source potential and the gate potential of the selectiontransistors 36 on the bit line side is small, and the selectiontransistors 36 are switched to the OFF state by a back gate effect.Thereby, the silicon pillars 31 are in a floating state and the bodypotential V_(body) of the selected cells is maintained at a high valueby coupling with the control gate electrodes CG provided with theintermediate potential V_(pass) (e.g., 10 V). Therefore, the difference(V_(pgm)−V_(body)) between the writing potential V_(pgm) (e.g., 18 V) ofthe control gate electrode CG of the selected cells and the bodypotential V_(body) decreases, and electrons are not injected into thecharge storage film 26. As a result, the value “1” is written into theselected cells.

For the unselected memory strings 38, the potential of the siliconpillars 31 is in the floating state because the selection transistors 36at both of the end portions are switched to the OFF state. In such acase, the body potential V_(body) of the silicon pillars 31 can becontrolled by the potential applied to the control gate electrodes CG,the voltage increase rate thereof, and the potential of the selectiongate electrodes SG; and a high potential can be maintained. As a result,the difference (V_(pgm)−V_(body)) between the gate potential and thebody potential of the memory transistors 35 decreases, electrons are notinjected into the charge storage film 26, and the initial value ismaintained.

Thus, in this embodiment, the writing row (the Y coordinate) is selectedby controlling the conducting state of the selection transistors, anddata is written to the memory strings 38 arranged in the X direction inorder by row. At this time, the potential of the control gate electrodesis controlled by block. Therefore, for the writing disturbance, it issufficient to consider the total time necessary for writing the data tothe memory strings in the block. Thereby, the disturbance time can becontrolled by adjusting the block size.

Because multiple pump circuits 45 are provided in the drive circuit 41in this embodiment as illustrated in FIG. 6, potentials having multiplelevels can be generated as the writing potential V_(pgm) as illustratedin FIG. 8. The writing potentials V_(pgm) generated by each of the pumpcircuits 45 can be applied to the control gate electrodes CG of each ofthe levels by each of the switch elements 47 of the switch circuit unit46 connecting each of the pump circuits 45 to the control gateelectrodes CG of each of the levels based on the control signal outputby the decoder 43. Thus, the values of the writing potential V_(pgm) candiffer by the level where the control gate electrode CG to which thepotential is to be applied is disposed.

In other words, as illustrated in FIG. 8, the value of the writingpotential V_(pgm) applied to a control gate electrode CG4 of theuppermost level, that is, the 4th level from the bottom, is set to be(V_(pgm) 0); the value of the writing potential V_(pgm) applied to acontrol gate electrode CG3 of the third level from the bottom is set tobe (V_(pgm) 0−ΔV_(pgm) 1) which is lower than (V_(pgm) 0); the value ofthe writing potential V_(pgm) applied to a control gate electrode CG2 ofthe 2nd level from the bottom is set to be (V_(pgm) 0−ΔV_(pgm) 2) whichis lower than (V_(pgm) 0−ΔV_(pgm) 1); and the value of the writingpotential V_(pgm) applied to a control gate electrode CG1 of thelowermost level is set to be (V_(pgm) 0−ΔV_(pgm) 3) which is lower than(V_(pgm) 0−ΔV_(pgm) 2). Here, 0<ΔV_(pgm) 1<ΔV_(pgm)2<ΔV_(pgm) 3.

Supposing that the values of the potentials applied to the control gateelectrodes CG are the same, the intensity of the electric field appliedto the tunneling film 27 increases as the surface area ratio of theinner surface and the outer surface of the charge storage film 26increases. Therefore, the intensity of the electric field applied to thetunneling film 27 increases as the diameter of the through-hole 21decreases. Thereby, an electron current due to tunneling may undesirablyflow into the tunneling film 27 of the memory transistor 35 to which thevalue of “0” is to be written; and a miswrite (a program disturbance)may occur in which the mistaken value of “1” is undesirably written.Moreover, even in the case where such a miswrite does not occur, theamount of electrons injected from the silicon pillar 31 into the chargestorage film 26 may increase for a memory transistor having a smallthrough-hole 21 diameter; and the amount of charge injected into thecharge storage film 26 undesirably becomes non-uniform.

Therefore, in this embodiment as described above, a writing potentialV_(pgm) having a lower potential is applied in memory transistorspositioned lower and having smaller through-hole 21 diameters. At thistime, the body potential V_(body) of the silicon pillar 31 is apotential near the reference potential Vss. Therefore, the potentialdifference (V_(pgm)−V_(body)) between the control gate electrode CG andthe silicon pillar 31 decreases as the memory transistor is disposedlower. Also, the electric field applied to the tunneling film 27decreases as the potential difference (V_(pgm)−V_(body)) decreases.

Thus, in this embodiment, the drive circuit 41 applies the writingpotential V_(pgm) that is lower as the control gate electrode CG isdisposed lower. Thereby, the increase of the electric field intensitycaused by smaller through-hole 21 diameters is canceled; and a moreuniform electric field intensity can be applied to the tunneling film27. As a result, miswriting (program disturbances) does not occur easilyeven for the memory transistors 35 disposed lower and having smallerthrough-hole 21 diameters. Further, the amount of electrons injectedinto the charge storage films 26 of the memory transistors 35 during onewriting operation can be uniform; and the driving of the memorytransistors can be stabilized. Because the amount of the injectedelectrons is made to be uniform, the writing operation duration of thememory transistors 35 also can be uniform. Thereby, the writingoperation duration of the entire device 1 can be reduced; and theoperation speed can be increased.

A method for determining the value of the writing potential V_(pgm) willnow be described. As illustrated in FIG. 9, the intensity of theelectric field applied to the tunneling film 27 in one memory transistorcan be uniform by determining the value of the writing potential V_(pgm)such that a potential difference V follows Formula 1 recited below,where r (μm) is the diameter of the through-hole 21 of the one memorytransistor and V is the potential difference (V_(pgm)−V_(body)) betweenthe control gate electrode CG and the silicon pillar 31. The value ofthe potential difference V illustrated in Formula 1 and FIG. 9 herein isa relative value such that the value of the potential difference V(i.e., V_(pgm)−V_(body)) is 1 when the diameter of the through-hole 21is 0.06 μm (60 nm). Formula 1 recited below provides an effectiveapproximation at least for values of r in the range of 0.05 to 0.1 μm.V=6999.4×r³−1971.3×r²+194.66×r−5.0952   Formula 1(Reading Operation)

A reading operation in which the data written to any of the memorytransistors 35 is read will now be described. As illustrated in FIG. 7,the drive circuit 41 applies the ON potential V_(on) to the back gateBG, and the back gate transistors 37 are switched to the ON state. Thedrive circuit 41 applies the ON potential V_(on) (e.g., 3.0 V) to theselection gate electrodes SGs and SGb of the selected strings, and theselection transistors 36 are switched to the ON state. On the otherhand, the drive circuit 41 applies the OFF potential V_(off) (e.g., 0 V)to the selection gate electrodes SGs and SGb of the unselected memorystrings 38, and the selection transistors 36 are switched to the OFFstate.

The drive circuit 41 applies a potential to the control gate electrodeCG of the selected cells, i.e., the control gate electrode CGb of thethird layer from the bottom, such that the conducting state differs dueto the value of the selected cells. The potential is, for example, thereference potential Vss (e.g., 0 V) and is a potential such that acurrent does not flow in the body in the case where the value of theselected cell is “0,” i.e., when electrons are stored in the chargestorage film 26 and the threshold is shifted to positive, and a currentflows in the body in the case where the value of the selected cell is“1,” i.e., when electrons are not stored in the charge storage film 26and the threshold is not shifted. For the memory transistors 35 otherthan those of the selected cells, a reading potential V_(read) (e.g.,4.5 V) is applied to the control gate electrodes thereof such that thememory transistors 35 are switched to the ON state regardless of thevalues thereof.

In this state, a potential Vb1 (e.g., 0.7 V) is applied to each of thebit lines BL, and the reference potential Vss (e.g., 0 V) is applied toeach of the source lines SL. As a result, a current flows in theselected string if the value of the selected cell is “1” and a currentdoes not flow in the selected string if the value of the selected cellis “0.” Accordingly, the value of the selected cell can be read bydetecting the current flowing in the source line SL from the bit line BLvia the selected string or by detecting the potential drop of the bitline BL. For example, because the potential of the bit line BL changeswhen the value of the selected cell is “1,” the change is amplified by abit line amplifier circuit (not illustrated) and detected; and thedetection result is stored as data in a data buffer (not illustrated).For the unselected memory strings 38, a current does not flow regardlessof the values stored in the memory transistors 35 because the selectiontransistors 36 are in the OFF state.

In this embodiment, the drive circuit 41 varies the value of the readingpotential V_(read) by the level where the control gate electrode CG towhich the potential is to be applied is disposed using the pump circuit45. In other words, as illustrated in FIG. 8, the value of the readingpotential V_(read) applied to the control gate electrode CG4 of theuppermost level, i.e., the 4th level from the bottom, is set to be(V_(read) 0); the value of the reading potential V_(read) applied to thecontrol gate electrode CG3 of the third level from the bottom is set tobe (V_(read) 0−ΔV_(read) 1) which is lower than (V_(read) 0); the valueof the reading potential V_(read) applied to the control gate electrodeCG2 of the 2nd level from the bottom is set to be (V_(read) 0−ΔV_(read)2) which is lower than (V_(read) 0−ΔV_(read) 1); and the value of thereading potential V_(read) applied to the control gate electrode CG1 ofthe lowermost level is set to be (V_(read) 0−ΔV_(read) 3) which is lowerthan (V_(read) 0−ΔV_(read) 2). Here, 0<ΔV_(read) 1<ΔV_(read) 2<ΔV_(read)3.

As described above, supposing that the same potential is applied to eachof the control gate electrodes CG, the intensity of the electric fieldapplied to the tunneling film 27 of each of the memory transistorsincreases as the through-hole 21 diameter decreases. In the case wherethe electric field applied to the tunneling film 27 during the readingoperation is too strong, electron current undesirably flows in thetunneling film 27 due to tunneling; and a phenomenon (read disturbance)occurs in which the value “0” written to the memory transistorundesirably changes to the value “1.”

Therefore, in this embodiment as described above, the reading potentialV_(read) has a lower potential as the control gate electrode CG ispositioned lower with a smaller through-hole 21 diameter. Thereby, theincrease of the electric field intensity caused by smaller through-hole21 diameters is canceled by reducing the reading potential V_(read); andthe electric field intensity applied to the tunneling film 27 is made tobe uniform. As a result, read disturbance of the memory transistor canbe prevented. It is favorable for the value of the reading potentialV_(read) to be determined according to Formula 1 recited above forreasons similar to those of the case of the writing operation describedabove.

(Erasing Operation)

An erasing operation in which data written to the memory transistor iserased will now be described. The unit of erasing data is by block. Asillustrated in FIG. 7, the drive circuit 41 applies the ON potentialV_(on) to the back gate BG, and the back gate transistors 37 areswitched to the ON state. The reference potential Vss (e.g., 0 V) isapplied to all of the control gate electrodes CG of the block to beerased (hereinbelow referred to as “selected block”). The potentials ofthe bit lines BL and the source lines SL are increased to an erasingpotential V_(erase) (e.g., 15 V). Also, the selection gate potentialV_(sg) which is lower than the erasing potential V_(erase) is applied tothe selection gate electrodes SGb and SGs. That is, V_(sg)<V_(erase).

Thereby, the potential of the bit lines BL and the source lines SL isthe erasing potential V_(erase) (e.g., 15 V), and the potential of theselection gate electrodes SGb and SGs is the selection gate potentialV_(sg). Therefore, a hole current is produced by tunneling between bandsdue to the potential difference between the bit lines BL and theselection gate electrodes SGb and the potential difference between thesource lines SL and the selection gate electrodes SGs; and the potentialof the silicon pillars 31, i.e., the body potential, increases. On theother hand, the reference potential Vss (e.g., 0 V) is applied to thecontrol gate electrodes CG of the block to be erased (the selectedblock). Therefore, holes are injected into the charge storage films 26of the memory transistors 35 due to the potential difference between thesilicon pillars 31 and the control gate electrodes CG, and electrons inthe charge storage film 26 undergo pair annihilation. As a result, thedata is erased. Although it is necessary to provide a potentialdifference between the erasing potential V_(erase) and the selectiongate potential V_(sg) sufficient to inject sufficient holes into thecharge storage film 26 because the body potential increases due to theinjection of the hole current, it is simultaneously necessary to adjustsuch that the gate insulating film 28 of the selection transistor 36 isnot destructed by an excessive potential difference.

On the other hand, for the blocks not to be erased (the unselectedblocks), the potential of the selection gate electrodes SGb and SGs isincreased to a potential approaching the potential of the bit lines BLand the source lines SL, and the electric field between a diffusionlayer connected to the bit lines BL or the source lines SL and theselection gate electrodes SGb or SGs is reduced so that a hole currentis not produced. Or, the potential of the control gate electrodes CG isincreased simultaneously with that of the silicon pillars 31 so thatholes in the silicon pillars 31 are not injected into the charge storagefilms 26. Thereby, the values already written to the memory transistors35 of the unselected blocks are maintained as-is.

In the erasing operation as well, when the drive circuit 41 supplies ahigher potential as the reference potential Vss as the control gateelectrode CG is disposed lower, the potential difference between thesilicon pillar 31 and the control gate electrode CG decreases as thememory transistor is disposed lower; and the electric field applied tothe ONO film 24 can be uniform. Thereby, the application of an excessiveelectric field to the memory transistors having small through-holediameters and the injection of electrons from the control gate electrodeCG into the charge storage film 26 due to tunneling during the erasingoperation can be prevented. As a result, the undesirable cancellation ofthe injection of the holes necessary for the erasing operation, that is,the hole injection from the silicon pillar 31 toward the charge storagefilm 26, by the reverse injection of electrons from the control gateelectrode CG toward the charge storage film 26 is prevented; and theerasing operation can be implemented reliably.

Effects of this embodiment will now be described.

According to this embodiment as described above, the drive circuit 41includes the multiple pump circuits 45; and each of the pump circuits 45is connected to the control gate electrodes CG of each of the levels viaeach of the switch elements 47. Thereby, mutually different drivingpotentials can be applied to the control gate electrodes CG of each ofthe levels. Thereby, the potential difference between the control gateelectrode CG and the silicon pillar 31 can be reduced as the memorytransistor is positioned lower and has a smaller through-hole 21diameter; and the electric field intensity applied to the ONO films 24of the memory transistors can be uniform. As a result, misoperation ofthe memory transistor can be prevented. Great effects can be obtained byapplying such technology to at least one operation selected from thewriting operation, the reading operation, and the erasing operation whensupplying the potential to the control gate electrode to provide thegreatest potential difference with the silicon pillar of the operation.

A second embodiment will now be described.

FIG. 10 schematically illustrates features of a nonvolatilesemiconductor memory device according to this embodiment.

In this embodiment as illustrated in FIG. 10, the through-hole has atwo-level configuration. In each level, the through-hole becomes finerdownward. In other words, the stacked body ML is made of two partialstacked bodies ML1 and ML2 arranged in the Z direction; and the partialstacked body ML2 is stacked on the partial stacked body ML1. Multipleinsulating films 15 and multiple electrode films 14 are stacked in eachof the partial stacked bodies ML1 and ML2. Each of a lower portion 21aof the through-hole 21 made in the partial stacked body ML1 and an upperportion 21b made in the partial stacked body ML2 have a taperedconfiguration that becomes finer downward. Therefore, the upper endportion of the lower portion 21a is wider than the lower end portion ofthe upper portion 21b; and a step is formed in the inner face of thethrough-hole 21 at the boundary portion between the lower portion 21aand the upper portion 21b.

The drive circuit 41 applies potentials to the multiple electrode films14 disposed in the partial stacked body ML1 such that the potentialdifference with the silicon pillar 31 decreases as the electrode film 14is disposed lower, that is, toward the silicon substrate 11 side.Similarly, the drive circuit 41 applies potentials to the multipleelectrode films 14 disposed in the partial stacked body ML2 such thatthe potential difference with the silicon pillar 31 decreases as theelectrode film 14 is disposed lower. Thereby, in this embodiment aswell, the fluctuation of the electric field intensity caused by thefluctuation of the through-hole 21 diameter can be compensated byvarying the driving potential; and the electric field intensitiesapplied to the ONO films 24 of the memory transistors 35 can be uniform.As a result, the misoperation of the memory transistor can be prevented.Otherwise, the configuration, operations, and effects of this embodimentare similar to those of the first embodiment described above.

Three or more levels of partial stacked bodies may be stacked. In such acase, it is sufficient for the drive circuit 41 to apply the potentialto the electrode film 14 (the control gate electrode CG) disposed ineach of the partial stacked bodies such that the potential differencewith the silicon pillar 31 decreases as the electrode film is disposedlower.

A third embodiment of the invention will now be described.

This embodiment is an embodiment of a method for manufacturing thenonvolatile semiconductor memory device 1 according to the firstembodiment described above.

FIG. 11 to FIG. 19 are cross-sectional views of processes, illustratingthe method for manufacturing the nonvolatile semiconductor memory deviceaccording to this embodiment.

FIG. 11 to FIG. 19 illustrate the same cross section as that of FIG. 3.

First, as illustrated in FIG. 11, the silicon substrate 11 is prepared.A memory cell region is set in the silicon substrate 11. A peripheralcircuit region (not illustrated) is set around the memory cell region.An element separation film is formed in a prescribed region of the upperlayer portion of the silicon substrate 11. Then, a thick film gateinsulating film for high breakdown voltage transistors and a thin filmgate insulating film for low breakdown voltage transistors are madeseparately in the peripheral circuit region. At this time, theinsulating film 10 is formed on the silicon substrate 11 also in thememory cell region.

Then, the polysilicon film 12 is deposited on the insulating film 10 asa conductive film with a thickness of, for example, 200 nm.Photolithography and RIE (Reactive Ion Etching) are performed on theupper layer portion of the polysilicon film 12 in the memory cell regionto make multiple trenches 52 having rectangular configurations alignedin the Y direction on the upper face of the polysilicon film 12. Thetrenches 52 are arranged in a matrix configuration along the X directionand the Y direction. The trenches 52 are recesses made in the upper faceof the polysilicon film 12.

Continuing as illustrated in FIG. 12, a silicon nitride film isdeposited by, for example, CVD (Chemical Vapor Deposition) to form asacrificial film 53 on the polysilicon film 12. At this time, thesacrificial film 53 also is filled into the trenches 52. Then, thesacrificial film 53 and the polysilicon film 12 are patterned by, forexample, photolithography and RIE. Thereby, the polysilicon film 12 inthe memory cell region is divided for every block 50 (referring to FIG.5); the back gates BG made of the polysilicon film 12 are formed inflat-plate configurations in each of the blocks 50; and gate electrodesmade of the polysilicon film 12 are formed in the peripheral circuitregion.

Subsequently, a spacer made of silicon oxide is formed and a diffusionlayer is formed by ion implantation in the peripheral circuit region.Then, an inter-layer insulating film is deposited in the peripheralcircuit region, planarized, and recessed so that the upper face thereofis the same height as the upper face of the polysilicon film 12. Then,the sacrificial film 53 is recessed so that the sacrificial film 53 isremoved from the polysilicon film 12 and left only in the interiors ofthe trenches 52.

Continuing as illustrated in FIG. 13, the insulating films 15 made of,for example, silicon oxide are deposited alternately with the electrodefilms 14 made of, for example, polysilicon on the back gate BG (thepolysilicon film 12) in the memory cell region to form the stacked bodyML.

Then, as illustrated in FIG. 14, the multiple through-holes 21 arecollectively made in the stacked body ML by dry etching such as RIE toalign in the Z direction. The through-holes 21 are arranged in a matrixconfiguration along the X direction and the Y direction. Also, thebottom portions of the through-holes 21 reach both end portions of thesacrificial films 53 filled into the trenches 52. Thereby, twothrough-holes 21 adjacent to each other in the Y direction reach each ofthe sacrificial films 53. The through-hole 21 has a circularconfiguration as viewed from the Z direction. At this time, the innerside face of the through-hole 21 unavoidably has a tapered configurationinclined with respect to the Z direction. As a result, the through-hole21 is made in an inverted circular-conic trapezoidal configurationbecoming finer downward such that the upper end portion is the widest.

Continuing as illustrated in FIG. 15, wet etching is performed via thethrough-holes 21 to remove the sacrificial film 53 (referring to FIG.14) from the trenches 52. Thereby, the trench 52 becomes thecommunicating hole 22; and one continuous U-shaped hole 23 is formed ofthe communicating hole 22 and the two through-holes 21 communicatingwith both end portions thereof.

Then, as illustrated in FIG. 16, a barrier film (not illustrated) madeof, for example, silicon nitride is formed; and subsequently, a siliconoxide film, a silicon nitride film, and a silicon oxide film arecontinuously deposited. Thereby, the blocking film 25 made of thesilicon oxide film, the charge storage film 26 made of the siliconnitride film, and the tunneling film 27 made of the silicon oxide filmare stacked in this order on the inner face of the U-shaped hole 23 viathe barrier film to form the ONO film 24.

Then, amorphous silicon is deposited on the entire surface. Thereby,amorphous silicon is filled into the U-shaped hole 23 to form theU-shaped silicon member 33. The U-shaped silicon member 33 is formedfrom the pair of silicon pillars 31 filled into the through-holes 21 andthe one connection member 32 filled into the communicating hole 22.Subsequently, the amorphous silicon, the silicon oxide film, the siliconnitride film, and the silicon oxide film deposited on the stacked bodyML are removed.

Continuing as illustrated in FIG. 17, the stacked body ML is patternedby, for example, RIE to make trenches 54 in the stacked body ML. Thetrench 54 is made to align in the X direction to link the regionsbetween the two silicon pillars 31 connected to the connection member 32and reach the insulating film 15 of the lowermost layer.

At this time, as illustrated in FIG. 5, the trenches 54 are made todivide the electrode films 14 into a pair of mutually meshed comb-shapedpatterns. In other words, the trenches 54 are made in the X-directioncentral portion of the stacked body ML to align in the X direction.Thereby, the electrode films 14 are divided into multiple control gateelectrodes CG aligned in the X direction. At this time, the trenches 54are not made in the regions directly above the regions between theconnection members 32 in the Y direction. Thereby, each of the controlgate electrodes CG is pierced by two of the silicon pillars 31 arrangedalong the Y direction. At both X-direction end portions of the stackedbody ML, the trenches 54 are not aligned in the X direction and are madeto align intermittently in the Y direction. Thereby, the control gateelectrodes CGb and CGs alternately disposed along the Y direction at theX-direction central portion of the stacked body ML have commonconnections to each other at each of the X-direction end portions of thestacked body ML.

Then, as illustrated in FIG. 18, an insulating film 16 is deposited onthe stacked body ML and planarized. The insulating film 16 also isfilled into the trenches 54. Then, the conductive film 17 made of, forexample, amorphous silicon is deposited, etched, and left only in thememory cell region.

Then, a resist film (not illustrated) is formed, for example, on theconductive film 17; and the stacked body ML is patterned into astairstep configuration by repeatedly performing etching using theresist film as a mask and performing slimming of the resist film.Thereby, both X-direction end portions of the control gate electrodes CGfor each level are not covered with the control gate electrodes CG ofthe level thereabove as viewed from above (the Z direction); and insubsequent processes, contacts can be formed from above to the controlgate electrodes CG of each level. Then, an etching stopper film (notillustrated) made of, for example, silicon nitride is formed to coverthe stacked body ML patterned into the stairstep configuration; aninter-layer insulating film (not illustrated) is formed thereupon; andthe upper face is planarized. Thereby, the inter-layer insulating filmis filled around the stacked body ML.

Subsequently, the insulating film 18 is formed on the conductive film17. The through-holes 51 are made to pierce the insulating film 18, theconductive film 17, and the insulating film 16 to reach the upper endsof the through-holes 21 in the stacked body ML.

Then, as illustrated in FIG. 19, an insulating film is deposited on theentire surface, and amorphous silicon is deposited. Etch-back isperformed on the amorphous silicon and the insulating film to leave theamorphous silicon and the insulating film only in the through-holes 51.Thereby, the gate insulating film 28 is formed on the inner face of thethrough-holes 51 and the amorphous silicon is filled. Then, heattreatment is performed at a temperature of, for example, 600° C. tocrystallize the amorphous silicon in the through-holes 51 to formpolysilicon. Ion implantation is performed on the polysilicon usingarsenic (As) with, for example, an acceleration voltage of 40 keV and adose of 3×10¹⁵ cm⁻² to form a drain diffusion layer (not illustrated).Thereby, the silicon pillars 34 are formed in the through-holes 51. Thesilicon pillars 34 connect to the silicon pillars 31.

Continuing, patterning by RIE and the like is performed on theinsulating film 18 and the conductive film 17 to make trenches 55aligned in the X direction in the regions between the silicon pillars 34adjacent to each other in the Y direction. Thereby, the conductive film17 is divided along the Y direction to form multiple selection gateelectrodes SG aligned in the X direction.

Then, as illustrated in FIG. 3, the insulating film 19 is formed on theinsulating film 18; source plugs SP are buried in the insulating film19; and the source lines SL are formed on the insulating film 19 toalign in the X direction. At this time, the source lines SL areconnected to the drain diffusion layers of some of the silicon pillars34 via the source plugs SR Contacts (not illustrated) are formed in theinter-layer insulating film (not illustrated) provided around thestacked body ML to connect to each of the control gate electrodes CG andeach of the selection gate electrodes SG from above. Then, theinsulating film 20 is formed on the insulating film 19 to cover thesource lines SL. Then, the bit plugs BP are buried in the insulatingfilms 20 and 19 and the bit lines BL are formed on the insulating film20 to align in the Y direction. At this time, the bit lines BL areconnected to the drain diffusion layers of the remaining silicon pillars34 via the bit plugs BP. On the other hand, the drive circuit 41(referring to FIG. 6) is formed in the peripheral circuit region bynormal methods. Thereby, the nonvolatile semiconductor memory device 1is manufactured.

According to this embodiment, the nonvolatile semiconductor memorydevice 1 according to the first embodiment described above can bemanufactured. According to this embodiment, the drive circuit 41supplies mutually different potentials to the control gate electrode CGof each of the levels. Thereby, the electric fields applied to the ONOfilms 24 of the memory transistors 35 are made to be uniform. Therefore,it is unnecessary to make the through-hole 21 diameters to beexcessively uniform. Therefore, the aspect ratio of the through-hole 21can be increased; the number of times that the through-holes 21 are madecan be reduced when manufacturing the device 1 in which the prescribednumber of levels of the electrode film 14 is stacked; and accordingly,the number of lithography processes can be reduced. As a result, themanufacturing cost of the nonvolatile semiconductor memory device 1 canbe reduced.

The series of processes described above forming the stacked body ML,making the through-hole 21 in the stacked body ML, and filling thesilicon pillar 31 into the through-hole 21 may be performed twice tomanufacture a nonvolatile semiconductor memory device 2 according to thesecond embodiment described above. By performing the processes describedabove three times or more, a nonvolatile semiconductor memory device canbe manufactured in which partial stacked bodies are stacked in threelevels or more. In other words, portions of the through-holes 21 made ineach of the partial stacked bodies are made collectively for the partialstacked body by dry etching.

Hereinabove, the invention is described with reference to exemplaryembodiments. However, the invention is not limited to these exemplaryembodiments. Additions, deletions, or design modifications of componentsor additions, omissions, or condition modifications of processesappropriately made by one skilled in the art in regard to the exemplaryembodiments described above are within the scope of the invention to theextent that the purport of the invention is included.

For example, although an example is illustrated in the first embodimentdescribed above in which the drive circuit 41 supplies mutuallydifferent potentials to the control gate electrodes CG of each of thelevels for each of the writing operation, the reading operation, and theerasing operation, the invention is not limited thereto. For example,mutually different potentials may be supplied to the control gateelectrodes of each of the levels only for the writing operation and thereading operation. In such a case, a common reference potential Vss maybe used; and the drive circuit can be simplified. Further, mutuallydifferent potentials may be supplied to the control gate electrodes ofeach of the levels only for one operation selected from the writingoperation, the reading operation, and the erasing operation. Theconfigurations of the control gate electrodes and the like are notlimited to those of the exemplary embodiments described above.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel devices and methods describedherein may be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the devices andmethods described herein may be made without departing from the spiritof the inventions. The accompanying claims and their equivalents areintended to cover such forms or modifications as would fall within thescope and spirit of the inventions.

The invention claimed is:
 1. A nonvolatile semiconductor memory device,comprising: a substrate; a stacked body provided on the substrate, thestacked body including a plurality of insulating films alternatelystacked with a plurality of electrode films, a through-hole being madein the stacked body to align in a stacking direction; a semiconductorpillar buried in an interior of the through-hole; a charge storage filmprovided between the electrode film and the semiconductor pillar; and adrive circuit supplying a potential to the electrode film, a diameter ofthe through-hole differing by a position in the stacking direction, thedrive circuit supplying a potential to reduce a potential differencewith the semiconductor pillar as a diameter of the through-hole piercingthe electrode film decreases.
 2. The device according to claim 1,wherein a diameter of the through-hole decreases toward the substrate.3. The device according to claim 2, wherein the through-holes are madecollectively by dry etching.
 4. The device according to claim 1, whereinthe stacked body includes a plurality of partial stacked bodies arrangedin the stacking direction, a plurality of the insulating films and aplurality of the electrode films being disposed in the partial stackedbody, and in each of the partial stacked bodies, a diameter of thethrough-hole decreases toward the substrate.
 5. The device according toclaim 4, wherein portions of the through-holes made in each of thepartial stacked bodies are made collectively for the partial stackedbody by dry etching.
 6. The device according to claim 1, wherein thethrough-hole has a circular configuration as viewed from the stackingdirection, and a potential provided by the drive circuit to one of theelectrode films is determined according toV=6999.4×r³−1971.3×r²+194.66×r−5.0952 where r (μm) is a diameter of aportion of the through-hole piercing the one electrode film, V is apotential difference between the one electrode film and thesemiconductor pillar, and V is a relative potential difference having apotential difference of 1 when the diameter is 0.06 μm.
 7. The deviceaccording to claim 1, wherein the drive circuit includes: a decoder tooutput a control signal; a pump circuit to increase a suppliedpotential; and a switch element to switch between connecting anddisconnecting the pump circuit and the electrode film based on thecontrol signal.
 8. The device according to claim 7, wherein the pumpcircuit and the switch element are provided for each of the electrodefilms.
 9. The device according to claim 1, further comprising: a backgate disposed between the substrate and the stacked body; and aconnection member provided in the back gate to connect two adjacentsemiconductor pillars to each other.
 10. The device according to claim1, wherein a memory cell region and a peripheral circuit region are setin the substrate, the semiconductor pillar and the charge storage filmare disposed in the memory cell region, and the drive circuit isdisposed in the peripheral circuit region.
 11. A method for driving anonvolatile semiconductor memory device, the device including: asubstrate; a stacked body provided on the substrate, the stacked bodyincluding a plurality of insulating films alternately stacked with aplurality of electrode films, a through-hole being made in the stackedbody to align in a stacking direction; a semiconductor pillar buried inan interior of the through-hole; and a charge storage film providedbetween the electrode film and the semiconductor pillar, a diameter ofthe through-hole differing by a position in the stacking direction, themethod comprising: when applying a potential to the electrode film,supplying a potential to reduce a potential difference with thesemiconductor pillar as a diameter of the through-hole piercing theelectrode film decreases.
 12. The method according to claim 11,comprising providing a potential to one of the electrode films, thepotential being determined according toV=6999.4×r³−1971.3×r²+194.66×r−5.0952 where r (μm) is a diameter of aportion of the through-hole piercing the one electrode film, V is apotential difference between the one electrode film and thesemiconductor pillar, and V is a relative potential difference having apotential difference of 1 when the diameter is 0.06 μm, the through-holehaving a circular configuration as viewed from the stacking direction.13. The method according to claim 11, wherein the potential is a writingpotential to inject an electron from the semiconductor pillar into thecharge storage film.
 14. The method according to claim 11, wherein thepotential is a reading potential to detect whether or not an electron isstored in the charge storage film.
 15. A nonvolatile semiconductormemory device comprising: a first memory cell transistor being above asemiconductor substrate; a second memory cell transistor being above thefirst memory cell transistor; a third memory cell transistor being abovethe second memory cell transistor; a first word line electricallyconnected to a gate of the first memory cell transistor; a second wordline electrically connected to a gate of the second memory celltransistor; a third word line electrically connected to a gate of thethird memory cell transistor; and a control circuit configured toperform a read operation on a condition that a second voltage is appliedto the second word line and a third voltage is applied to the third wordline when a read operation for the first memory cell transistor isperformed, a first voltage is applied to the first word line and thethird voltage is applied to the third word line when a read operationfor the second memory cell transistor is performed, and the firstvoltage is applied to the first word line and the second voltage isapplied to the second word line when a read operation for the thirdmemory cell transistor is performed, and the first voltage being lowerthan the second voltage and the third voltage being lower than the firstvoltage.
 16. The device according to claim 15, further comprising: afourth memory cell transistor being above the third memory celltransistor; and a fourth word line electrically connected to a gate ofthe fourth memory cell transistor, wherein the control circuit isconfigured to perform a read operation on a condition that a fourthvoltage is applied to the fourth word line when the read operation forthe first memory cell transistor is performed, when the read operationfor the second memory cell transistor is performed and when the readoperation for the third memory cell transistor is performed, and thefourth voltage is higher than the third voltage and lower than the firstvoltage.
 17. The device according to claim 15, wherein the first memorycell transistor includes a first portion of a semiconductor body, thesecond memory cell transistor includes a second portion of thesemiconductor body, the third memory cell transistor includes a thirdportion of the semiconductor body, a first diameter of the first portionis smaller than a second diameter of the second portion and a thirddiameter of the third portion is smaller than the first diameter.
 18. Anonvolatile semiconductor memory device, comprising: a substrate; afirst electrode film provided on the substrate, the first electrode filmbeing spaced from the substrate; a second electrode film provided on thefirst electrode film, the second electrode film being spaced from thefirst electrode film; a third electrode film provided on the secondelectrode film, the third electrode film being spaced from the secondelectrode film; a semiconductor pillar intersecting the first electrodefilm, the second electrode film and the third electrode film, a firstportion of the semiconductor pillar being disposed in the firstelectrode film, a second portion of the semiconductor pillar beingdisposed in the second electrode film and a third portion of thesemiconductor pillar being disposed in the third electrode film, a firstdiameter of the first portion being smaller than a second diameter ofthe second portion and a third diameter of the third portion beingsmaller than the first diameter; a charge storage film provided betweenthe semiconductor pillar and the first electrode film, between thesemiconductor pillar and the second electrode film and between thesemiconductor pillar and the third electrode film; and a drive circuitsupplying a first potential to the first electrode film, supplying asecond potential to the second electrode film and supplying a thirdpotential to the third electrode film, the first potential being lowerthan the second potential and the third potential being lower than thefirst potential.
 19. The device according to claim 18, furthercomprising: a fourth electrode film provided on the third electrodefilm, the fourth electrode film being spaced from the third electrodefilm, the semiconductor pillar intersecting the fourth electrode film, afourth portion of the semiconductor pillar being disposed in the fourthelectrode film, a fourth diameter of the fourth portion being smallerthan the first diameter and larger than the third diameter, and thedrive circuit supplying a fourth potential to the fourth electrode film,the fourth potential being lower than the first potential and higherthan the third potential.
 20. The device according to claim 18, whereina step is formed on a side surface of the semiconductor pillar at aboundary between the second portion and the third portion.
 21. Thedevice according to claim 18, wherein the drive circuit includes: adecoder to output a control signal; a pump circuit to increase asupplied potential; and a switch element to switch between connectingand disconnecting the pump circuit and one of the first electrode film,the second electrode film and the third electrode film based on thecontrol signal.